Journals

2023

2. Kumari Neeraj Kaushal and Nihar R. Mohapatra, “A Physics-Based Compact Model to Capture Cryogenic Behavior of LDMOS Transistors”, IEEE Transactions on Electron Devices, Early Access, 2023.

1. Rutu Patel, Ravi Hegde and Nihar R. Mohapatra, “Surrogate Models for Device Design using Simple Efficient Deep Learning”, Solid State Electronics, Vol. 199, January 2023.

2022

6. K. Nidhin, Suresh Balanethiram, Deleep Nair, Rosario D’Esposito, Nihar R. Mohapatra, S. Fregonese, Thomass Zimmer and Anjan Chakravorty, “BEOL Thermal Resistance Extraction in SiGe HBTs”, IEEE Transactions on Electron Devices, Vol. 69, Isue 12, 6541-6546, 2022.

5. Rutu Patel and Nihar R. Mohapatra,“Novel step field plate RF LDMOS transistor for improved BVDS Ron tradeoff and RF performance”, IEEE Transactions on Electron Devices, Vol. 69, Issue 8, pp. 4401-4107, 2022.

4. Kumari Neeraj Kaushal, Virender Dan and Nihar R. Mohapatra,“Scalable substrate current model for LDMOS transistors based on internal drain voltage”, IEEE Transactions on Electron Devices, Vol. 69, Issue 8, pp. 4095-4101, 2022.

3. Satyajit Mohapatra and Nihar R Mohapatra,”Dispersion in Placements: Quantification and Insights”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 41, Issue 8, pp. 2380-2392, 2022.

2. Kumari Neeraj Kaushal and Nihar R. Mohapatra,”Unified theory of the capacitance behavior in LDMOS devices”, IEEE Transactions on Electron Devices, Vol. 69, Issue 1, pp. 39-44, 2022.

1. Mohit D. Ganeriwala, Aishwarya Singh, Abhilash Dubey, Ramandeep Kaur and Nihar R. Mohapatra,”A bottom-up scalable compact model for quantum confined nanosheet FETs”, IEEE Transactions on Electron Devices, Vol. 69, Issue 1, pp. 380-387, 2022.

2021

4. Mohit D. Generiwala, Francisco G. Ruiz, Enrique G. Marin and Nihar R. Mohapatra,”A unified compact model for electrostatics of III-V GAA transistors with different geometries”, Journal of Computational Electronics, Vol. 20, Issue 5, pp. 1676-1684, 2021.

3. Biplob Nath, Samit Barai, Pardeep Kumar and Nihar R. Mohapatra,”A novel ML augmented DRC framework for identification of yield detractor patterns”, IEEE Transactions on Semiconductor Manufacturing, Vol. 34, Issue 3, pp. 379-386, 2021.

2. Abdul Ghaffar, Mohit D. Ganeriwala, Kenta Hongo, Ryo Maezono and Nihar R. Mohapatra, “Insights into the mechanical and electrical properties of metal-phosphorene interface: An ab-initio study with wide range of metals”, ACS Omega, March 2021.

1. Kumari Neeraj Kaushal and Nihar R. Mohapatra, “A zero-cost technique to improve ON-state performance and reliability of power LDMOS transistors”, IEEE Journal of Electron Devices Society (IEEE JEDS), Vol. 9, pp. 334-341, 2021.

2020

5. Satyajit Mohapatra and Nihar R. Mohapatra, “The gradient error compensation in SC-MDACs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 39, Issue 12, pp. 4359-4374, December 2020.

4. Mandar Bhoir, Thomas Chiarella, Jerome Mitrad, Naoto Horiguchi and Nihar R. Mohapatra, “Vt extraction methodologies influence process-induced Vt variability: Does this fact still hold for advanced technology nodes?”, IEEE Transactions on Electron Devices (IEEE TED), VOl. 67, no. 11, pp. 4691-4695, Nov. 2020.

3. Mandar S. Bhoir, Nihar R. Mohapatra,”Effects of scaling on analog FoMs of UTBB FD-SOI MOS transistors”, IEEE Transactions on Electron Devices (IEEE TED), Vol. 67, Issue 8, pp. 3035, 2020.

2. Pardeep Duhan, Ramgopal Rao, Nihar R. Mohapatra, “Effect of device dimensions, layout and pre-gate carbon implant on hot carrier induced degradation in HKMG nMOS transistors”, IEEE Transactions on Device and Materials Reliability (IEEE TDMR), VOl. 20, Issue 3, pp. 555, 2020.

1. Tanmay Chavan, Sangya Dutta, Nihar R. Mohapatra and Udayan Ganguly, “Band to band tunnelling based ultra-energy efficient silicon neuron”, IEEE Transactions on Electron Devices (IEEE TED), Vol. 67, Issue 6, pp. 2614, 2020.

2019

8. Mandar Bhoir, Kumari Neeraj Kaushal, Soumya Panda, Amit Singh, H. S. Jatata and Nihar R. Mohapatra, “Source Underlap - A novel technique to improve safe operating area and output-conductance in LDMOS transistors”, IEEE Transaction on Electro Devices (IEEE TED), Vol. 66, Issue 11, pp. 4823, 2019.

7. Mandar Bhoir, Thomas Chiarella, Lars Ake Ragnarsson, Jerome Mitrad, Valentina Terzeiva, Naoto Horiguchi and Nihar R. Mohapatra, “Analog Performance and its Variability in Sub-10nm Fin-width FinFETs - A Detailed Analysis”, IEEE Journal of Electron Devices Society (JEDS), Vol. 7, pp. 1217, 2019.

6. Mohit D. Ganeriwala, Francisco G. Ruiz, Enrique G. Marin, Nihar R. Mohapatra, A Compact Model for the III-V Nanowire Electrostatics including Band Nonparabolicity, Journal of Computational Electronics, Vol. 18, Issue 4, pp. 1229, 2019.

5. Apoorva Ojha and Nihar R. Mohapatra, “A computationally efficient quantum-corrected poisson solver for accurate device simulation of multi-gate FETs”, Solid State Electronics, Vol. 160, October 2019.

4. Sangya Dutta, Tanmay Chavan, Nihar R. Mohapatra and Udayan Ganguly, “Electrical Tunability of Partially Depleted Silicon on Insulator (PD-SOI) Neuron”, Solid State Electronics, Vol. 160, October 2019.

3. Rohit Dawar, Samit Barai, Pardeep Kumar, Babji Srinivasan and Nihar R. Mohapatra, “Random forest based robust classification for lithographic hotspot detection”, Journal of Micro-Nanolithography, MEMS, and MOEMS (JM3), Apr. 2019.

2. Mandar Bhoir, Yogesh Singh Chauhan and Nihar R. Mohapatra, Back-gate Bias and Substrate Doping influenced Substrate Effect in UTBB FD-SOI MOS Transistors: Analysis and Optimization Guidelines, IEEE Transaction on Electro Devices (IEEE TED), Vol. 66, Issue 2, pp. 861, 2019.

1. Mohit D. Ganeriwala, Francisco G. Ruiz, Enrique G. Marin, Nihar R. Mohapatra, A Compact Charge and Surface Potential Model for III-V Cylindrical Nanowire Transistors, IEEE Transaction on Electro Devices (IEEE TED), Vol. 66, Issue 1, pp. 73, 2019.

2018

6. Sangya Dutta, Tinish Bhattacharya, Nihar R Mohapatra, Manan Suri and Udayan Ganguly, Transient Variability in SOI based LIF Neuron and Impact on Unsupervised Learning, IEEE Transaction on Electron Devices (IEEE TED), Vol 65, pp. 5137, 2018..

5. Pardeep Kumar, Babji Srinivasan and Nihar R Mohapatra, Sample Plan Selection Techniques for Lithography Process Model Building, Journal of Micro-Nanolithohraphy, MEMS and MOEMS (JM3), Vol. 17, pp. 043501, 2018.

4. Apoorva Ojha and Nihar R. Mohapatra, A Computationally Efficient Compact Model for Trap-Assisted Carrier Transport through Multi-stack Gate Dielectrics of HKMG nMOS transistors, Journal of Electron Devices Society (JEDS), Vol. 6, pp. 1164, 2018.

3. Sangya Dutta, T. Chavan, S. Shukla, V. Kumar, A. Shukla, Nihar R. Mohapatra and Udayan Ganguly, Dynamics, Design and Application of a Silicon-on-Insulator Technology based Neuron, MRS Advances, 2018.

2. Pardeep Kumar, Alan E Rosenbluth, Ramana Pusuluri, Ramya Viswanathan, Babji Srinivasan and Nihar R. Mohapatra, Multiple Stages of Regression to Improve Accuracy in calibrated Lithography Process, Journal of Micro/Nanolithohraphy, MEMS and MOEMS (JM3), Vol. 17, pp. 023503, 2018.

1. Hari Shanker Gupta, Satyajit Mohapatra, Nisha Pandya, Nihar R. Mohapatra, Rohit Vasoliya and Arup Roy Chowdhury, CFCS Calibration Circuit Design for Multi-bit Pipelined ADC Architectures, Microsystem Technologies, pp. 1, 2018.

2017

4. Mohit D. Ganeriwala, Chandan Yadav, Francisco G Ruiz, Enrique G Marin, Yogesh Singh Chauhan and Nihar R. Mohapatra, Modeling od Quantum Confinement and Capacitance in III-V Gate All Around 1D Transistors, IEEE Transaction on Electron Devices (IEEE TED), Vol. 64, Issue 12, pp. 4889, 2017.

3. Pardeep Duhan, V. Ramgopal Rao and Nihar R. Mohapatra, PBTI in HKMG nMOS Transistors - Effect of Width, Layout and other Technological Parameters, IEEE Transactions on Electron Devices (IEEE-TED), Vol. 64, Issue 10, pp. 4018, 2017.

2. Sangya Dutta, Vinay Kumar, Aditya Shukla, Nihar R. Mohapatra and Udayan Ganguly, Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET, Scientific Reports, Vol. 7, Issue 1, pp. 8257, 2017.

1. Chandan Yadav, Mohit D. Ganeriwala, Nihar R. Mohapatra, Amit Agarwal and Yogesh Singh Chauhan, Compact Modeling of Gate Capacitance in III-V Channel Quadruple-Gate FETs, IEEE Transactions on Nanotechnology (IEEE TNANO), Vol. 16, Issue 4, pp. 1, July 2017.

2016

3. Mohit D. Ganeriwala, Chandan Yadav, Nihar R. Mohapatra, Sourabh Khandelwal, Chenming Hu and Yogesh Singh Chauhan, Modeling of charge and quantum capacitance in low effective mass III-V MOSFETs, Journal of Electron Devices Society (JEDS), Vol. 4, No. 6, pp. 396, November 2016.

2. Nihar R. Mohapatra, Mohit D. Ganeriwala and Satya Siva Naresh, Effect of pre-gate carbon implant on narrow width behavipr and performance of High-K metal gate nMOS transistors, IEEE Transaction on electron Devices (IEEE TED), Vol. 63, July 2016.

1. Apoorva Ojha, Y. S. Chauhan and Nihar R. Mohapatra, A Physics-Based Compact Model for the Threshold Voltage of Strained HKMG nMOS Transistors, Journal of Electron Devices Society (JEDS), Vol. 4, Issue. 2, pp. 42, February 2016.

2015

4. Satya Siva Naresh, Pardeep duhan and Nihar R. Mohapatra, Role of Device Dimensions and Layout on the Analog Performance of Gate First HKMG NMOS Transistors, IEEE Transaction on electron Devices (IEEE TED), Vol. 62, pp. 3792, November 2015.

3. Pardeep Duhan, Mohit Ganeriwala, V. Ramgopal Rao and Nihar R. Mohapatra, Anomalous Width Dependence of Gate Current in High-K Metal Gate NMOS Transistors, IEEE Electron Device Letters (IEEE EDL), Vol. 36, Issue 8, pp.739, August 2015.

2. Pardeep Kumar, Babji Srinivasan and Nihar R. Mohapatra, Fast and Accurate Lithography Simulation using Cluster Analysis in Resist Model Building, Journal of Micro-Nanolithography, MEMS, MOEMS (JM3), Vol. 14, Issue 2, pp. 023506, April-June 2015.

1. Satya Siva Naresh and Nihar R. Mohapatra, Analysis and Modeling of Narrow Width Effect in Gate-First HKMG NMOS Transistors, IEEE Transaction on Electron Devices (IEEE TED), Vol. 62, pp.1085, April 2015.

2012

1. Amey M. Walke, Nihar R. Mohapatra, Effects of Small Geometries on the Performance of Gate First High-K Metal Gate NMOS Transistors, IEEE Transaction on Electron Devices (IEEE TED), Vol. 59, Issue 10, pp.2582, October 2012.

2004

2. V. Ramgopal Rao, Nihar R. Mohapatra, Device and circuit performance issues with deeply scaled High-K MOS transistors, Journal of Semiconductor Technology and Science, Vol. 4, pp. 52-62, March 2004.

1. Deleep R. Nair, Nihar R. Mohapatra, S. Mahapatra, S. Shukuri and J. D. Bude, Effect of P and E scaling on drain disturb in flash EEPROMs under CHE and CHISEL operation, IEEE Transaction on Devices and Materials Reliability (IEEE TDMR), Vol. 4, Issue 1, pp. 52, March 2004.

2003

2. Nihar R. Mohapatra, Deleep R. Nair, S. Mahapatra, V. Ramgopal Rao, S. Shukuri and J. D. Bude, CHISEL Programming Operation of Scaled NOR Flash EEPROMs - Effect of Voltage scaling, Device scaling and Technological Parameters, IEEE Transaction on Electron Devices (IEEE TED), Vol. 50, issue 10, pp. 2104, Oct 2003.

1. Nihar R. Mohapatra, Madhav P. Desai, Siva G. Narendra and V. Ramgopal Rao, Modeling of Parasitic Capacitance in Deep Sub-Micrometer Conventional and High-K Gate Dielectric MOS Transistors, IEEE Transaction on Electron Devices (IEEE TED), Vol. 50, Issue 4, pp. 959, April 2003.

2003

1. Nihar R. Mohapatra, Madhav P. Desai, Siva G. Narendra and V. Ramgopal Rao, The Impact of High-K Gate Dielectrics on Deep Sub-Micrometer CMOS Device and Circuit Performance, IEEE Transaction on Electron Devices (IEEE TED), Vol. 49, Issue 5, pp.826, May 2002.