Recent Updates

6th June 2022 - Rutu's paper titled “Novel step field plate RF LDMOS transistor for improved BVDS Ron tradeoff and RF performance” is accepted for publication in IEEE TED. Congratulations Rutu.

26th May 2022 - Neeraj and Virender's paper titled “Scalable substrate current model for LDMOS transistors based on internal drain voltage” is accepted for publication in IEEE TED. Congratulations to both of them.

11th April 2022 - Om Maheshwari received the prestigious PMRF Fellowship. He is the second student from our research group to get this. Congratulations Om.

1st December 2021 - Neeraj's paper titled “Unified theory of the capacitance behaviour in LDMOS devices” is accepted for publication in IEEE TED. Congratulations Neeraj.

17th November 2021 - Mohit and Aishwarya's paper titled “A bottom-up scalable compact model for quantum confined nanosheet FETs” is accepted for publication in IEEE TED. Congratulations to both of them.

22nd October 2021 - D Sharda Devi received the prestigious PMRF Fellowship. She is the first student from our research group to get this. Congratulations Sharda.

20th July 2021 - Mohit's paper titled “A unified compact model for electrostatics of III-V GAA transistors with different geometries” is accepted for publication in Journal of Computational Electronics. Congratulation Mohit.

May 2021 - Biplob and Pardeep's paper titled “A Novel ML Augmented DRC Framework for Identification of Yield Detractor Patterns” is accepted for publication in IEEE Transactions on Semiconductor Manufacturing. Congratulations to both of them.

25th February 2021 - Abdul's paper titled “Insights into the mechanical and electrical properties of metal phosphorene interface: An abinitio study with a wide range of metals” is accepted for publication in ACS Omega. Congratulation Abdul.

16th February 2021 - Satyajit Mohapatra successfully defended his PhD thesis. Congratulations Satyajit.

8th February 2021 - Neeraj's paper titled “A zero-cost technique to improve ON-state performance and reliability of power LDMOS transistors” is accepted for publication in IEEE-JEDS. Congratulations Neeraj.

17th September 2020 - Mandar's paper titled “Vt extraction methodologies influence process-induced Vt variability: Does this fact still hold for advanced technology nodes?” is accepted for publication in IEEE-TED. Congratulations Mandar.

23rd August 2020 - Mandar S Bhoir received the Award for the Outstanding Research (PhD) in the 9th CONVOCATION of IIT Gandhinagar. Congratulations Mandar.

3rd August 2020 - Mandar S Bhoir successfully defended his PhD thesis. Congratulations Mandar.

23rd July 2020 - Mohit D Ganeriwala successfully defended his PhD thesis. Congratulations Mohit.

3rd Juy 2020 - Pardeep's paper titled “Effect of device dimensions, layout and pre-gate carbon implant on hot carrier induced degradation in HKMG nMOS Transistors” is accepted for publication in IEEE-TDMR. Congratulations Pardeep.

1st Juy 2020 - Mandar's paper titled “Effects of scaling on analog FoMs of UTBB FDSOI MOS transistors” is accepted for publication in IEEE-TED. Congratulations Mandar.

13th June 2020 - Mandar's paper titled “Effects of scaling on analog FoMs of UTBB FDSOI MOS transistors” is accepted for publication in IEEE-TED. Congratulations Mandar.

11th April 2020 - Nihar is elevated to the grade of Senior Member IEEE. IEEE Senior Membership is an honour bestowed only to those who have made significant contributions to the profession.

30th March 2020 - Tanmay and Sangya's paper titled “Band-to-Band Tunnelling based Ultra-Energy Efficient Silicon Neuron” is accepted for publication in IEEE-TED. Congratulations to Tanmay and Sangya.

18th March 2020 - Mohit received the Outstanding Graduate Teaching Fellow Award from IIT Gandhinagar. The award is given to recognise his excellent contributions to the course “EE 644: Physics of Transistors” as an instructor. Congratulations to Mohit.

5th March 2020 - Satyajit's paper titled “The Gradient Error Compensation in SC-MDACs” is accepted for publication in IEEE-TCAD. Congratulations to Satyajit.

20th December 2019 - Mandar received the Best Poster Award for his paper titled “The impact of technology scaling on Analog performance of UTBB FDSOI transistors” at IWPSD 2019. Congratulations to Mandar.

16th December 2019 - Mandar's paper titled “Process-induced Vt Variability in Nanoscale FinFETs: Does Vt Extraction Methods Have Any Impact” is accepted for Oral presentation at EDTM 2020. Congratulations to Mandar.

16th December 2019 - Mohit's paper titled “Significance of L-valley Charges and a Method to Include It in Electrostatic Model of III-V GAA FETs” is accepted for Oral presentation at EDTM 2020. Congratulations to Mohit.

16th December 2019 - Apoorva's paper titled “Corrections to WKB Approximation for Accurate Calculation of Gate Current in HKMG MOS Transistors” is accepted for Poster presentation at EDTM 2020. Congratulations to Apoorva.

16th September 2019 - Mandar and Neeraj's paper titled “Source Underlap - A Novel Technique to improve Safe Operating Area and Output-Conductance in LDMOS Transistors” is accepted for publication in IEEE-TED. Congratulations to Mandar and Neeraj.

15th September 2019 - Satyajit's paper titled “The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD)” is accepted for Oral presentation at The 33rd International Conference on VLSI Design (VLSID 2020). Congratulations to Satyajit.

13th September 2019 - Mandar's paper titled “Variability sources in nanoscale bulk FinFETs and TiTaN - a promising low variability WFM for 7nm and 5nm CMOS nodes” is accepted for Oral presentation at IEDM 2019. This paper is among 7 outstanding papers selected this year to be presented at the CMOS Platform technologies Session of the Advanced Logic Section of the conference. This is a very good achievement for our lab. Congratulations to Mandar.

11th September 2019 - Mandar received the Outstanding Graduate Teaching Fellow Award from IIT Gandhinagar. The award is given to recognise his excellent contributions to the course “ES 104: Introduction to Analog and Digital Electronics,” as a tutor. Congratulations to Mandar.

7th August 2019 - Mandar's paper titled “Analog Performance and its Variability in Sub-10nm Fin-width FinFETs: A Detailed Analysis” is accepted for publication in Journal of Electron Devices Society. Congratulations to Mandar.

31st July 2019 - Mohit's paper titled “A Compact Model for the III-V Nanowire Electrostatics including Band Nonparabolicity” is accepted for publication in Journal of Computational Electronics. Congratulations to Mohit.

5th July 2019 - Apoorva Ojha successfully defended her PhD thesis. Congratulations to Apoorva.

24th June 2019 - Apoorva's paper titled “A Computationally Efficient Quantum-Corrected Poisson Solver for accurate Device Simulation of Multi-Gate FETs” is accepted for publication in Solid State Electronics. Congratulations to Apoorva.

9th May 2019 - Pardeep Kumar successfully defended his PhD thesis. Congratulations to Pardeep.

17th April 2019 - Rohit's paper titled “Random Forest Based Robust Classification for Lithographic Hotspot Detection” is accepted for publication in SPIE JM3. Congratulations to Rohit.

27th Feb 2019 - Mohit's paper titled “A Compact Charge and Surface Potential Model for III-V Quadruple Gate FETs with Square Geometry” received the Silver Leaf Award at MOS-AK 2019 held at IIT Hyderabad (25 - 27 February 2019). Congratulations to Mohit.

29th Dec 2018 - Sarath and Mohit's paper titled “Capacitance and Surface Potential Model for III-V Double-Gate FET” is accepted for oral presentation at ISDCS 2019 to be held at Hiroshima University during 6-8 March 2019. Congratulations to Sarath and Mohit.

19th Dec 2018 - Mohit and Sarath's paper titled “A Simple Charge and Capacitance Model for Asymmetric III-V DGFETs using CCDA” received the Best Manuscript Award at 4th ICEE held at Bangalore during 17-19 December 2019. Congratulations to Mohit and Sarath.

17th Dec 2018 - Mandar's paper titled “Back-gate Bias and Substrate Doping influenced Substrate Effect in UTBB FD-SOI MOS Transistors: Analysis and Optimization Guidlines” is accepted for publication in IEEE-TED. Congratulations to Mandar.

7th Dec 2018 - Mandar's paper titled “Effect of Sub-10nm FIn-widths on the Analog Performance of FinFETs” is accepted for oral presentation at 3rd Electron Devices Technology and Manufacturing (EDTM) Conference 2019. The conference will be held in Singapore during 12-15 March 2019.

24th Sept 2018 - Two papers from group are accepted (Oral presentation) for 32nd International Conference on VLSI Design. The acceptance rate of papers is 26%. The conference will be held in Delhi during 5-9 January 2019.

24th Sept 2018 - Pardeep’s paper titled “Sample Plan Selection Techniques for Lithography Process Model Building” is accepted for publication in JM3 (SPIE).

15th Sept 2018 - Sangya’s paper titled “Transient Variability in SOI based LIF Neuron and Impact on Unsupervised Learning” is accepted for publication in IEEE-TED. Congratulations to Sangya.

7th Sept 2018 - Apoorva’s paper titled “A Computationally Efficient Compact Model for Trap-Assisted Carrier Transport through Multi-stack Gate Dielectrics of HKMG nMOS Transistors” is accepted for publication in IEEE-JEDS. Congratulations to Apoorva.

18th August 2018 - Mohit’s paper titled “A Compact Charge and Surface Potential Model for III-V Cylindrical Nanowire Transistors” is accepted for publication in IEEE-TED (Special Issue on Compact Modelling). Congratulations to Mohit.

30th July 2018 - Ramandeep and Rutu joined the group as PhD students.

11th July 2018 - Our project titled “Developing Low Cost Bipolar Transistors for Analog and RF Applications” is approved for funding under SERB-EMR scheme. This work will be done in collaboration with Prof. Anjan Chakravorty's team at IIT Madras.

5th June 2018 - Satyajit's paper is accepted for ORAL presentation in the 61st IEEE International Midwest Symposium on Circuits and Systems (MWCAS), Windsor, Canada. Title - “The Hotspot Compensation in High Speed Data Converters”. Congratulations to Satyajit.

24th May 2018 - Mandar's ASCENT proposal is accepted. He will spend 3months in IMEC, Belgium starting 18th June 2018.

21st April 2018 - Satyajit's paper is accepted for POSTER presentation in the 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China. Title - “Mismatch Resilient 3.5-bit MDAC with MCS-CFCS”. Congratulations to Satyajit.

1st january 2018 - Nihar received the prestigious JSPS Invitational Fellowship - Short Term to visit Japan and visit several universities in Summer 2018.