Conference Proceedings

2023

1. Ramandeep Kaur and Nihar R. Mohapatra, “Process-Induced Uniaxial Strain in Naosheet-FET Based CMOS Technology – Is It Still Beneficial”, Accepted for Oral Presentation, IEEE EDTM 2023, Seoul, South Korea, 2023.

2022

4. Om Maheshwari, Ravins Katiyar, Amitava Dasgupta, Anjan Chakravorty, Deleep R. Nair and Nihar R. Mohapatra, “An Indigenous Low-Cost Robust BiCMOS Process Flow for NavIC Applications”, 6th IEEE International Conference on Emerging Electronics, Bengaluru, India, Dec 11-14, 2023. This paper received the “Best Paper” award.

3. Aishwarya Singh, Mohit D. Ganeriwala, Ramandeep Kaur and Nihar R. Mohapatra, “A Simplified Approach to Include Confinement Induced Band Structure Changes into Compact Model of NsFETs”, 6th IEEE International Conference on Emerging Electronics, Bengaluru, India, Dec 11-14, 2023. This paper received the “Best Poster” award.

2. Anuj Srivastava, Nishant Kumar, Nihar R. Mohapatra and Hari Shanker Gupta,”High Resolution Temperature Sensor Signal Processing ASIC for Cryo-Cooler Electronics”, 26th International Symposium on VLSI Design and Test (VDAT), Jammu, India, July 17-19, 2022.

1. Rutu Patel and Nihar R. Mohapatra, ”Low-cost, CMOS integrable step filed plate RF LDMOS transistor with low IM3 distortion and high drain efficiency”, IEEE Electron Device Technology and Manufacturing (EDTM) Conference, Oita, Japan, March 6-9, 2022.

2021

2. Kumari Neeraj Kaushal and Nihar R. Mohapatra, ”Behavior of LDMOS transistors at cryogenic temperature – An experiment based analysis”, 25th International Symposium on VLSI Design and Test (VDAT), Surat, India, September 16-18, 2021.

1. Shubham Patil, Kumari Neeraj Kaushal, Mandar Bhoir and Nihar R. Mohapatra, “Physics-Based Parameter Extraction Methodology for Channel Doping Gradient (CDG) LDMOS Transistors Based on HiSIM-HV2 Model”, IEEE Electron Device Technology and Manufacturing (EDTM) Conference, Chengdu, China, March 9-12, 2021.

2020

4. Shubham Pande, S. Balanethiram, A. K. Singh, H. S. Jatana, Nihar R. Mohapatra and Anjan Chakravorty, “Development of low-cost silicon BJT technology and modeling”, International Conference on Emerging Electronics (ICEE), New Delhi, India, November 2020.

3. Mohit D. Ganeriwala, Francisco G. Ruiz, Enrique G. Marin, Nihar R. Mohapatra, “Significance of L-valley charges and a method to include it in electrostatic model of III-V GAA FETs”, IEEE Electron Device Technology and Manufacturing (EDTM) Conference, Penang, Malaysia, March 15-18, 2020.

2. Mandar Bhoir, Thomas Chiarella, Jerome Mitrad, Naoto Horiguchi and Nihar R. Mohapatra, “Process-induced VT variability in nanoscale FinFETs: Does VT extraction methods have any impact?”, IEEE Electron Device Technology and Manufacturing (EDTM) Conference, Penang, Malaysia, March 15-18, 2020.

1. Satyajit Mohapatra and Nihar R. Mohapatra, “The design of ultra-low power SAR ADC for implantable cardioverter defibrillator (ICD)”, 33rd International Conference on VLSI Design (VLSID), Bengaluru, India, January 4-8, 2020.

2019

10. Sarathchandran G. M., Mohit D. Ganeriwala and Nihar R. Mohapatra, “Charge and capacitance model for III-V independent gate FETs”, XXth International Workshop on Physics of Semiconductor Devices, Kolkata, India, December 17-20, 2020.

9. Mandar Bhoir and Nihar R. Mohapatra, “The impact of technology scaling on analog performance of UTBB FD-SOI MOS transistors”, XXth International Workshop on Physics of Semiconductor Devices, Kolkata, India, December 17-20, 2020.

8. Mandar Bhoir, Thomas Chiarella, Lars Ake Ragnarsson, Jerome Mitrad, Naoto Horiguchi and Nihar R. Mohapatra, “Variability sources in nanoscale bulk FinFET and TiTaN - a promising low variability WFM for 7nm and 5nm CMOS nodes”, IEDM 2019. This paper is among the 7 outstanding papers of the conference.

7. Yadukrishnan M., Satyajit Mohapatra and Nihar R. Mohapatra, “Design and Calibration of 14-bit 10KS-s Low Power SAR ADC for Biomedical Applications”, 2019 International Symposium on VLSI Design and Test, Indore, India, 2019. This paper received the “Best Paper” award.

6. S. Balanethiram, S. Pande, A. K. Singh,B. Umapathi, H. S. Jatana, Nihar R. Mohapatra and A. Chakravorty, “Development of Low-Cost Silicon BiCMOS Technology for RF Applications”, 2019 IEEE International Conference on Modeling of Systems Circuits and Devices (MOS-AK India 2019), Hyderabad, India, 2019.

5. Mohit D. Ganeriwala, Enrique G. Marin, Francisco G. Ruiz and Nihar R. Mohapatra, “A Compact Charge and Surface Potential Model for III-V Quadruple-Gate with Square Geometry”, 2019 IEEE International Conference on Modeling of Systems Circuits and Devices (MOS-AK India 2019), Hyderabad, India, 2019.

4. Mandar Bhoir, Nihar R. Mohapatra, Thomas Chiarella, Lars Ake Ragnarsson, Jerome Mitrad, Valentina Terzeiva and Naoto Horiguchi, “Effect of Sib-10nm Fin-Width on the Analog Performance of FinFETs”, 3rd Electron Devices Technology and Manufacturing (EDTM) Conference 2019, Singapore, 2019.

3. Sarathchandran GM, Mohit D. Ganeriwala and Nihar R. Mohapatra, “Capacitance and Surface Potential Model for III-V Double-Gate MOSFETs”, 2nd International Symposium on Devices, Circuits and Systems (ISDCS 2019), Hiroshima, Japan, 2019.

2. Satyajit Mohapatra, Hari Shanker Gupta, Nihar R. Mohapatra, Nisha Pandya, Sanjeev Mehta and Arup Roy Chowdhury, “A Mismatch Resilient 16-bit 20MS-s Pipelined ADC”, 32nd International Conference on VLSI Design, Delhi, 2019.

1. Amratansh Gupta, Mohit D. Ganeriwala and Nihar R. Mohapatra, “An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors”, 32nd International Conference on VLSI Design, Delhi, 2019.

2018

6. Mohit D. Ganeriwala, Sarathchandran GM., Nihar R. Mohapatra, “A Simple Charge and Capacitance Compact Model for Asymmetric III-V DGFETs using CCDA”, 4th IEEE International Conference on Emerging Electronics, Bangalore, 2018 (Best Manuscript Award).

5. Tanmay Chavan, Sangya Dutta, Nihar R Mohapatra and Udayan Ganguly, “An ultra energy efficient Neuron enabled by tunnelling in sub-threshold regime on a highly manufacturable 32nm SOI CMOS technology”, 76th Device Research Conference, USA, 2018.

4. Satyajit Mohapatra and Nihar R. Mohapatera, “The HotSpot Compensation in High Speed Data Converters”, 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Windsor, Ontario, Canada, 2018.

3. Satyajit Mohapatra, Hari Shanker Gupta and Nihar R. Mohapatra, “Mismatch Resilient 3.5-bit MDAC with MCS-CFCS”, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong SAR, China, 2018.

2. Mohit D. Ganeriwala, Enrique G. Marin, Francisco G. Ruiz and Nihar R. Mohapatra, “Computationally Efficient Analytic Charge Model for III-V Cylindrical Nanowire Transistors”, Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon 2018, Granada, Spain,March 2018.

1. Mandar S. bhoir and Nihar R. Mohapatra, “Impact of BOX Thickness and Ground-plane on non-linearity of UTBB FDSOI MOS Transistors”, Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon 2018, Granada, Spain, March 2018.

2017

6. Subrahmanya Teja, Mandar S. Bhoir and Nihar R. Mohapatra, “Split-Gate Architecture for higher Breakdown Voltage in STI based LDMOS Transistors”, 13th IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC), Hsinchu, Taiwan, October 2017.

5. Neelam Surana, Joycee Mekie and Nihar R. Mohapatra, “Impact of High-k Spacer on Circuit Level Performance of Junctionless FinFETs”, 13th IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC), Hsinchu, Taiwan, October 2017.

4. Jatindeep Singh, Satyajit Mohapatra and Nihar R. Mohapatra, “Performance optimized 64b-66b Line Encoding Technique for High Speed SERDES Devices”, 21st International Symposium on VLSI Design and TEST (VDAT), Roorkee, India, June 2017.

3. Ashish Soni, Abhijit Umap and Nihar R. Mohapatra, “Low-Power Sequential Circuit Design using Work-function Engineered FinFETs”, 21st International Symposium on VLSI Design and Test (VDAT), Roorkee, India, June 2017. (Best Paper Award)

2. Mandar Bhoir, Pragya Kushwaha, Yogesh S. Chauhan and Nihar R. Mohapatra, “Impact of substrate on the frequency behavior of trans-conductance in ultrathin body and BOX FDSOI MOS devices: a physical insight”, International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, Taiwan, April 2017.

1. Satyajit Mohapatra, Hari Shanker Gupta, Jatindeep Singh and Nihar R. Mohapatra, “A 64b-66b Line Encoding for High Speed Serializers”, 30th International Conference on VLSI Design, Hyderabad, India, January 2017.

2016

5. Pragya Kushwaha, Harshit Agarwal, Yogesh Chauha, Mandar Bhoir and Nihar R. Mohapatra, Sourabh Khandelwal, Juan P Duarte, Yen-Kai Lin, Huan-Lin Chang, and Chenming Hu, “Predictive effective mobility model for FDSOI transistors using technology parameters”, International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug. 2016.

4. Apoorva Ojha and Nihar R. Mohapatra, “An Improved model for Tunneling Probability in HKMG MOS transistors with correction in WKB Approximation”, 48th IEEE Semiconductor Interface Specialists Conference, San Diego, USA, December 2016.

3. Pardeep Duhan, V. Ramgopal Rao and Nihar R. Mohapatra, “Width and layout dependence of HC and PBTI induced degradation in HKMG nMOS transistors”, IEEE International Reliability Physics Symposium, Pasadena, USA, April 2016.

2. Hari Shanker Gupta, Satyajit Mohapatra, Nihar R. Mohapatra and Dinesh Kumar Sharma, “Novel design of a silicon photodetector and its integration in a 4x4 CMOS pixel array”, 17th International Symposium on Quality Electronics Design (ISQED), USA, March 2016.

1. Apoorva Ojha, Narendra Parihar and Nihar R. Mohapatra, “Analysis and Modeling of Stress Over Layer induced Threshold Voltage shift in HKMG nMOS Transistors”, 29th International Conference on VLSI Design, Kolkata, India, January 2016.

2015

3. Pardeep Kumar, Alan E. Rosenbluth, Babji Srinivasan, Ramya Viswanathan and Nihar R. Mohapatra, “Lithography Process Model Building Using Locally Linear Embedding”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington DC, USA, September 2015.

2. Pardeep Duhan, Nihar R. Mohapatra and Sharad Kumar Jain, “Width Dependence of HCI and PBTI in HKMG NMOS Transistors”, Proceedings of ICMAT and IUMRS, Singapore, June 2015.

1. Nihar R. Mohapatra, Satya Siva Naresh and Pardeep Duhan, “Analog Performance of Gate-First HKMG NMOS Transistors Role of Device Dimensions and Layout”, International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, Taiwan, April 2015.

2014

2. Ashita Chandnani and Nihar R. Mohapatra, “Design and Analysis of Piezoresistive Polyimide Nanocantilevers for Surface Stress Sensing Applications”, International Conference on MEMS and Sensors, Madras, India, Dec. 2014.

1. Ritesh Jain, Holger Ruecker and Nihar R. Mohapatra,“Optimization of Si MOS Transistors for THz detection using TCAD simulation”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Yokohoma, Japan, June 2014.

2013

3. Pardeep Kumar, Samit Barai, Babji Srinivasan and Nihar R. Mohapatra, “Process Model Accuracy Enhancement Using Cluster Based Approach”, International Workshop on Physics of Semiconductor Devices (IWPSD), Delhi, India, December 2013.

2. Satya Siva Naresh, Nihar R. Mohapatra and Pardeep Duhan, “Effects of HfO2 and Lanthanum capping Layer Thickness on Narrow Width Behavior of Gate First High-K Metal Gate NMOS Transistors”, International Conference on Solid State Device and Materials, Fukuoka, Japan, September 2013.

1. Pardeep Kumar, Babji Srinivasan and Nihar R. Mohapatra, “Nonlinear PCA for Source Optimization in Optical Lithography”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Glasgow, UK, June 2013.

2010

1. R. Gupta, F. Nemati, S. Robbins, K. Yang, V. Gopalakrishnan, R. Chopra, H. J. Cho, W. P. Maszara, Nihar R. Mohapatra, J. Wuu, D. Weiss and S. Nakib, “32nm High-Density High-Speed T-RAM Embedded Memory Technology”, International Electron Device Meeting (IEDM), San Francisco, USA, December 2010.

2009

1. Nihar R. Mohapatra, R. VanBentum, E. Pruefer, W. P. Maszara, C. Calliat, Z. Chalupa, Z. Johnson and D. Fisch, “Effect of SourceDrain Asymmetry on the Performance of Z-RAM Devices”, IEEE SOI Conference/, California, USA, October 2009.

2006

1. Nihar R. Mohapatra, H. Ruecker, K. E. Ehwald, R. Sorge, R. Barth, P. Schley, D. Schmidt and H. E. Wulf, “A Complimentary RF LDMOS Architecture Compatible with 0.13mm CMOS Technology”, 18th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Naples, Italy, June 2006.

2005

1. Nihar R. Mohapatra, K. E. Ehwald, R. Barth, H. Ruecker, D. Bolze, P. Schley, D. Schmidt and H. E. Wulf, “The Impact of Channel Engineering on the Performance and Reliability of LDMOS transistors”, European Solid State Device Research Conference (ESSDERC), Grenoble, France, September 2005.

2004

1. H. Ruecker, B. Heinemann, R. Barth, D. Bolze, J. Drews, O. Frusenko, T. Grabolla, U. Haak, W. Hoppner, D. Knoll, S. Marschmeyer, Nihar R. Mohapatra, H. H. Richter, P. Schley, D. Schmidt, B. Tillack, G. Weidner, D. Wolansky and H. E. Wulf, “Integration of High Performance SiGe:C HBTs with Thin-film SOI CMOS”, International Electron Device Meeting, USA, December 2004.

2003

7. Deleep R. Nair, Nihar R. Mohapatra, S. Mahapatra, S. Shukuri and J. D. Bude, “Effect of scaling on the reliability of flash EEPROMs under CHISEL programming”, 34th IEEE Semiconductor Interface Specialists Conference, Washington D.C, USA, December 2003.

6. Deleep R. Nair, Nihar R. Mohapatra, S. Mahapatra and S. Shukuri, “The impact of technology parameters and scaling on the programming performance and drain disturb in CHISEL flash EEPROMs”, International Conference on Solid State Device and Materials, Tokyo, Japan, September 2003.

5. Deleep R. Nair, Nihar R. Mohapatra, S. Mahapatra, S. Shukuri and J. D. Bude, “The Effect of CHE and CHISEL Programming Operation on Drain Disturb in Flash EEPROMs”, 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, 2003.

4. Nihar R. Mohapatra, Souvik Mahapatra, V. Ramgopal Rao, S. Shukuri, “The Impact of Channel Engineering on the Performance, Reliability and Scaling of CHISEL NOR Flash EEPROMs”, European Solid State Device Research Conference (ESSDERC), Lisbon, Portugal, September 2003.

3. Nihar R. Mohapatra, Souvik Mahapatra, V. Ramgopal Rao, S. Shukuri and J. D. Bude, “Effect of Programming Biases on the Reliability of CHE and CHISEL Flash EEPROMs”, International Reliability Physics Symposium (IRPS), Dallas, USA, April 2003.

2. Nihar R. Mohapatra, Madhav P. Desai and V. Ramgopal Rao, “Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics”, 16th International Conference on VLSI Design, Delhi, India, Jan 2003.

1. D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil and V. Ramgopal Rao, “Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor Circuits”, 16th International Conference on VLSI Design, Delhi, India, Jan 2003.

2002

3. Nihar R. Mohapatra, Souvik Mahapatra and V. Ramgopal Rao, “The study of Damage Generation in n-channel MOS Transistors Operated in the Substrate Enhanced Gate Current Regime”, 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, 2002.

2. Nihar R. Mohapatra, Madhav P. Desai, Siva G. Narendra and V. Ramgopal Rao, “Effect of technology scaling on MOS transistor performance with high-K gate dielectrics”, MRS Proceedings, San Fransisco, USA, 2002.

1. Krishna K. Bhuwalka, Nihar R. Mohapatra, Siva G. Narendra and V. Ramgopal Rao, “Effective Dielectric Thickness Scaling for high-K Gate Dielectric MOSFETs”, MRS Proceedings, San Fransisco, USA, 2002.

2001

4. Nihar R. Mohapatra, Souvik Mahapatra and V. Ramgopal Rao, “A comparative study of scaling properties of MOS transistors in CHE and CHISEL injection”, International Workshop on Physics of Semiconductor Devices (IWPSD), Delhi, India, December 2001.

3. Nihar R. Mohapatra, Souvik Mahapatra and V. Ramgopal Rao, “Study of degradation in CHISEL injection regime”, European Solid State Device Research Conference (ESSDERC), Munich, Germany, September 2001.

2. Nihar R. Mohapatra, Madhav P. Desai, Siva G. Narendra and V. Ramgopal Rao, “The impact of high-K gate dielectrics on sub 100nm CMOS circuit performance”, European Solid State Device Research Conference (ESSDERC), Munich, Germany, September 2001.

1. Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai and V. Ramgopal Rao, “Effect of Fringing Capacitance in Sub-100nm MOSFETs with high-K gate dielectrics”, 14th International Conference on VLSI Design, Bangalore, India, Jan 2001.